Signal Integrity / Power Integrity Engineer

About the role

Altera is looking for a Signal and Power Integrity Engineer to join its SERDES Analog team in Haifa. The role focuses on integrating mixed‑signal and high‑speed SERDES IPs into silicon, packages and PCBs, providing an excellent opportunity for early‑career engineers to develop hands‑on design skills.

Key responsibilities

• Support SERDES IP system simulation, including reference channel definition and parameter extraction under senior guidance.
• Review and validate silicon IP parameters together with package and PCB designs according to interface specifications.
• Participate in package and PCB schematic and layout reviews, analyze simulation results and help debug failing simulations.
• Apply signal and power integrity concepts to mixed‑signal and channel simulations for optimizing package and PCB designs.
• Assist in meeting power, performance and signal integrity requirements to ensure designs are implementation‑ready.
• Collaborate with internal teams to ensure successful integration of IPs, packages and PCBs.

Required profile

• B.Sc or M.Sc in Electrical Engineering from a recognized university.
• Strong background in electromagnetic and wave theory.
• Highly motivated junior engineer with relevant university project experience.
• Team player who enjoys tackling big challenges.
• Ability to study and apply theory across analog and digital electronics, signal and power integrity domains.
• Applicants must submit an academic grades sheet.

Required skills

• Experience in ASIC package design, including pin‑out optimization, stack‑up creation and high‑speed routing.
• Knowledge of silicon floor planning, signal integrity (SI) and power integrity (PI) considerations.
• Hands‑on experience with advanced test equipment such as oscilloscopes and TDR/VNA analyzers.
• Understanding of high‑speed signal design and power distribution networks (PDN).