Senior Logic/DSP Design Engineer – Mixed Signal

About the role

Altera is looking for a senior Logic/DSP Design Engineer to develop digital logic and DSP algorithms for mixed‑signal IP blocks in next‑generation FPGA products. The role bridges digital and analog domains, turning system‑level specifications into synthesizable RTL.

Key responsibilities

• Design and implement RTL for mixed‑signal subsystems such as calibration state machines, digital filters, adaptive equalization, and clock/data recovery loops.
• Collaborate with analog teams to define digital‑analog interfaces, calibration flows, and control logic.
• Perform RTL‑to‑gate synthesis, timing closure, and apply low‑power design techniques.
• Build and maintain verification environments (Verilog) for mixed‑signal verification and AMS co‑simulation.
• Support silicon bring‑up, debug digital logic against analog measurements, and mentor junior engineers.

Required profile

• BSc/MSc in Electrical Engineering with at least 7 years of digital logic design experience.
• Strong background in mixed‑signal or DSP projects and solid understanding of DSP fundamentals.
• Experience working closely with analog designers on digital‑analog co‑design.

Required skills

• Verilog RTL design and synthesis flow.
• DSP fundamentals (filtering, sampling, quantization, timing recovery).
• Mixed‑signal verification methodologies (AMS simulation, Verilog‑AMS, real‑number modeling).
• High‑speed SerDes, PCIe, DisplayPort, Ethernet interface knowledge.
• Calibration/adaptation algorithms for ADC/DAC or equalizers.
• Low‑power design techniques and static timing analysis (STA).