VLSI Team Lead

About the role

We are seeking a technical, execution‑focused VLSI Team Lead to spearhead the microarchitecture, logic design, and implementation of custom AI inference acceleration blocks. The role blends hands‑on RTL development with leadership of a small, agile engineering team in a fast‑paced startup environment.

Key responsibilities

• Lead and mentor a small front‑end VLSI team, define milestones, assign tasks, conduct design reviews and ensure on‑time delivery of silicon.
• Architect and write high‑performance, synthesizable RTL (SystemVerilog) for AI accelerator blocks and high‑bandwidth interconnects.
• Partner with compiler and embedded software teams to analyze data‑center workloads and refine microarchitecture for peak compute utilization.
• Own front‑end integration including synthesis, linting, CDC analysis, and initial static timing analysis to optimize power, performance and area.
• Coordinate with verification engineers to review test plans, close coverage gaps and troubleshoot complex debug scenarios.

Required profile

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field.
• 7+ years of ASIC/IC design experience with at least 2 years of leadership or mentoring.
• Proven track record of delivering tape‑out ready blocks for AI inference workloads.
• Ability to thrive in a fast‑paced startup environment and balance technical excellence with aggressive timelines.

Required skills

• SystemVerilog / Verilog RTL design.
• ASIC/IC front‑end flow: synthesis, linting, CDC, STA, PPA optimization.
• Experience with high‑speed memory interfaces (HBM, DDR) and PCIe.
• Integration of custom compute blocks with RISC‑V or ARM subsystems.
• Proficiency with Synopsys, Cadence or Siemens EDA tools.