Senior System and Chip Architect

Key responsibilities

• Define and own the architecture for key subsystems of Axonica's AI inference SoC — compute fabric, memory hierarchy, interconnect, and I/O from concept through tape-out.
• Translate brain‑inspired and novel compute paradigms into concrete microarchitecture, working closely with algorithm and AI research teams to keep the hardware faithful to the underlying computational model.
• Lead architecture‑level trade‑off analysis across power, performance, area (PPA), memory bandwidth, and latency, and defend those trade‑offs with data.
• Design, build, and use performance and power simulation models (C++, SystemC, or Python) to explore the architecture design space and validate decisions before RTL exists.
• Use AI‑assisted tools and workflows to accelerate specification writing, design‑space exploration, and architecture testing and validation.
• Contribute to Axonica's IP and patent portfolio.
• Mentor other architects and engineers as the architecture team grows.

Required profile

• 7+ years of experience in system or chip architecture for AI/ML accelerators, GPUs, DSPs, CPUs, or other high‑performance compute silicon at a company that has shipped production silicon.
• Hands‑on experience architecting chips from a clean sheet, defining novel microarchitecture and system design from first principles, with multiple tape‑outs.
• Deep fundamentals in computer architecture: pipelines, memory hierarchies, interconnect/NoC design, and dataflow or non‑von‑Neumann compute architectures.
• Understanding of AI/ML workloads—DNN and transformer inference, quantization, sparsity—and how algorithmic choices map to hardware efficiency and power.
• Skilled in building architecture‑level simulation models (performance, power, or cycle‑approximate) to explore trade‑offs and validate decisions ahead of RTL.
• Experience using AI‑assisted or AI copilot tools to define architecture specifications and to test and validate architecture.
• Comfort working across the algorithm/hardware boundary, partnering with RTL, verification, and software/compiler teams.
• BSc or MSc in Electrical Engineering, Computer Engineering, Computer Science, or related field (PhD a plus) and excellent communication skills.

Required skills

• C++
• SystemC
• Python
• AI‑assisted design tools
• Architecture‑level simulation (performance, power, cycle‑approximate)