Senior ASIC Design Engineer

About the role

Cisco Silicon One is looking for a Senior ASIC Design engineer to join its Front-End Design team, which covers the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff and validation. The team develops large-scale, advanced devices using cutting-edge silicon technologies and methodologies.

Key responsibilities

• Write and review micro-architecture specifications
• Implement RTL (Verilog/SystemVerilog) to meet timing, performance and power requirements
• Contribute to full chip integration, timing methodology and analysis
• Collaborate with verification engineers to resolve bugs and achieve coverage closure
• Work with the physical design team to close timing and PnR issues
• Support design methodology evolution and best practices
• Perform debug, root-cause analysis and post-silicon validation in the lab

Required profile

• B.Sc. or M.Sc. in Electrical Engineering from a top university
• RTL design experience

Required skills

• Familiarity with UVM and functional verification methodologies
• Preferred: experience with MATLAB simulations and bit-exact modeling environments
• Preferred: familiarity with mixed-signal systems and environments
• Preferred: hands-on knowledge of Clock Domain Crossing (CDC)