Design Verification (DV) Team Leader – AI Inference Hardware

About the role

We are seeking a highly technical, execution‑focused Design Verification (DV) Team Lead to architect, lead, and drive the verification ecosystem for our custom AI inference platform. You will act as a player‑coach, combining hands‑on testbench development with leadership of an agile verification team through block, SoC, multi‑die, and pre‑silicon tape‑out phases.

Key responsibilities

• Lead, mentor and scale an agile team of DV engineers, define verification milestones and enforce quality standards.
• Architect and develop modular UVM‑based verification environments for block‑level and top‑level SoC verification.
• Validate multi‑die/chiplet configurations using UCIe or BoW protocols and ultra‑high‑speed network fabrics (100G‑1.6T Ethernet, PCIe Gen5‑Gen7).
• Verify complex memory subsystems (DDR, LPDDR6, LPDDR6x, HBM) and ensure coverage closure through assertion‑based verification, constrained‑random testing and functional/code coverage.
• Collaborate with embedded software teams to enable early co‑verification on emulation platforms or C/C++ reference models.

Required profile

• Bachelor’s or Master’s in Electrical/Computer Engineering with 7+ years ASIC/SoC verification experience, including 2+ years leading engineers.
• Proven ability to thrive in a fast‑paced startup environment, balancing aggressive tape‑out timelines with thorough verification coverage.
• Strong understanding of AI compute clusters, matrix‑multiplication blocks, tensor units and asynchronous data paths.

Required skills

• UVM and SystemVerilog expertise.
• ASIC/SoC verification, constrained‑random verification, SVA (assertion‑based) methodology.
• Experience with UCIe, Bunch of Wires (BoW), PCIe Gen5/6/7, Ethernet 100G‑1.6T.
• Memory interface verification (DDR, LPDDR6, LPDDR6x, HBM).
• EDA tools: Synopsys VCS/Verdi, Cadence Xcelium, Siemens Questa.
• Emulation platforms and C/C++ reference model integration.