Micro-Architect – Networking (Google Cloud)

About the role

Google’s AI and Infrastructure team is seeking a senior Micro‑Architect to lead the design of networking ASICs that power Google Cloud services. You will work on custom silicon solutions, driving performance, efficiency and integration for next‑generation hardware experiences.

Key responsibilities

• Lead design activities for IP blocks, subsystems and full SoCs, defining interfaces, block diagrams and transaction flows.
• Develop and debug RTL in Verilog, SystemVerilog or VHDL, and perform functional and performance simulations.
• Run synthesis, timing, power analysis and FPGA/silicon bring‑up, including lint, CDC, FV and UPF checks.
• Collaborate with software teams to optimise hardware/software interfaces and ensure low‑latency, high‑throughput networking.
• Produce test plans, coverage analysis and verification strategies at block and SoC level.

Required profile

• 8+ years of experience architecting networking ASICs from specification to production.
• 4+ years of technical leadership experience.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science or related field, or equivalent practical experience.

Required skills

• RTL design in Verilog, SystemVerilog, VHDL.
• Procedural programming: C++, Python, Go.
• Networking protocols: TCP/IP, Ethernet, PCIe, DRAM.
• NoC principles and protocols: AXI, ACE, CHI.
• Experience with RDMA, packet processing, synthesis, timing closure, power analysis, FPGA bring‑up, lint/CDC/FV/UPF.

What we offer

• Opportunity to shape hardware that powers products used by millions worldwide.
• Work in a cutting‑edge environment with Google’s leading AI and cloud infrastructure.
• Flexible location choice between Tel Aviv and Haifa, Israel.