Micro-Architect, Networking, Google Cloud

About the role

Google’s AI and Infrastructure team is seeking a senior Micro‑Architect to lead the design of networking ASICs that power Google Cloud services. You will work on custom silicon solutions, driving performance, efficiency, and integration for products used by billions worldwide.

Key responsibilities

• Lead design activities for IP blocks, subsystems, and full SoCs.
• Define block‑level specifications, interface protocols, block diagrams, transaction flows, and pipelines.
• Develop and debug RTL code in Verilog, SystemVerilog, and VHDL, including functional and performance simulation.
• Run lint, CDC, functional verification, and UPF checks, and participate in synthesis, timing, and power closure.
• Collaborate with software teams to optimise hardware/software interfaces and ensure low‑latency, high‑throughput designs.

Required profile

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 8+ years of experience architecting networking ASICs from specification to production.
• 4+ years of technical leadership experience.
• Proven experience in micro‑architecture, design verification, logic synthesis, and timing closure.

Required skills

• RTL development in Verilog, SystemVerilog, VHDL.
• Hardware description and verification tools (lint, CDC, FV, UPF).
• Procedural programming: C++, Python, Go.
• Networking protocols: TCP/IP, Ethernet, PCIe, DRAM.
• Network‑on‑Chip concepts and protocols: AXI, ACE, CHI.
• Experience with RDMA, packet processing, and hardware offload design.

What we offer

• Opportunity to shape next‑generation hardware for Google’s global services.
• Collaborative environment with top‑tier engineers and researchers.
• Competitive compensation and benefits.