Junior DFT Engineer (Design for Test)

About the role

We are looking for a Junior Design‑for‑Test (DFT) Engineer to join Cisco’s DFT team in Israel. You will help embed test structures into silicon designs, ensuring that chips are fully testable and manufacturable.

Key responsibilities

• Insert DFT logic into RTL, run synthesis and Automatic Test Pattern Generation (ATPG) to guarantee hardware testability.
• Perform gate‑level simulations, timing checks and Design Rule Checks (DRC) to maintain design integrity.
• Execute regression suites and conduct deep‑dive debugging of simulation failures.
• Collaborate in a small, agile team that provides direct mentoring and rapid professional growth.

Required profile

• B.Sc or M.Sc in Electrical or Computer Engineering from a leading Israeli university with an average grade above 85.
• Team‑player who enjoys tackling big challenges and can quickly ramp up on interdisciplinary domains.

Required skills

• DFT logic insertion and synthesis.
• Automatic Test Pattern Generation (ATPG).
• Gate‑level simulation, timing analysis and DRC checks.
• Regression testing and debugging of hardware verification flows.

What we offer

• Opportunity to work at Cisco, a global leader in networking and AI‑driven infrastructure.
• Mentoring in a close‑knit team with broad professional development prospects.