ASIC Engineer - Front-End Design

cisco · Tel Aviv-Yafo

New

Senior 🇬🇧 English

UVM Functional verification MATLAB Clock Domain Crossing (CDC) RTL design Mixed-signal

Job description

About the role

Cisco is looking for an ASIC Engineer to join its Silicon One Front-End Design team, which sits at the heart of Cisco's silicon development. Engineers on the team cover the full spectrum of chip design, from definition and architecture through RTL design, verification, signoff and validation. The team uses advanced silicon technologies to develop large-scale, advanced devices.

Key responsibilities

Review micro-architecture specifications
Implement a UVM-based verification environment
Collaborate with design engineers to resolve bugs and achieve coverage closure
Work with firmware and lab teams to verify chip flows
Perform debug, root-cause analysis and post-silicon validation in the lab

Required profile

B.Sc. or M.Sc. in Electrical Engineering from a top university
4+ years of experience in the field

Required skills

Knowledge of UVM and functional verification methodologies
Preferred: experience with MATLAB simulations and bit-exact modeling environments
Preferred: familiarity with mixed-signal systems and environments
Preferred: hands-on knowledge of Clock Domain Crossing (CDC)

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Published 18 hours ago

Expires 1 month from now

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cisco

Tel Aviv-Yafo

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