Design Verification Engineer for DFT

About the role

Cisco's Design for Test (DFT) group delivers end-to-end DFT solutions for its flagship products, including Cisco Silicon One, which powers next-generation network devices and advanced AI workloads. The team works in a hybrid model, three days a week in the office in Midtown Tel Aviv or Caesarea. The role focuses on establishing and growing DFT design verification activity in the Cisco SiliconOne DFT team, for engineers with experience in DV roles who want to learn DFT design, verification methodologies and testability validation.

Key responsibilities

• Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.
• Develop verification plans, environments, checkers, assertions and coverage models for DFT features.
• Verify DFT architecture and implementation with DFT, design, architecture and verification teams.
• Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers and related SoC-level test features.
• Debug complex pre-silicon issues across RTL, verification environments and DFT logic.
• Contribute to scalable methodologies, reusable components and best practices, and bridge general DV methods with DFT-specific needs.

Required profile

• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering or a related field.
• 5+ years of experience in design verification roles.
• Strong experience with SystemVerilog and UVM-based verification environments.
• Experience developing verification plans, coverage models, assertions and debug flows.
• Strong communication skills and ability to work with cross-functional teams.
• Motivation to learn DFT concepts and preferred familiarity with scan insertion, memory BIST, ATPG, boundary scan and silicon test flows.
• Preferred: experience with complex SoC, networking or high-performance AI silicon, and system-level understanding of large chip architectures.