Principal Engineer – Memory IP Applications

About the role

As a Principal Engineer in Memory IP Applications, you will guide customers through the integration of Synopsys memory subsystem IPs into their ASIC/SoC designs. You will act as a technical advisor, troubleshoot complex issues, and ensure successful silicon bring‑up.

Key responsibilities

• Provide hands‑on technical guidance and support for integrating Synopsys Memory Sub System IPs, including RTL simulation, synthesis, floorplanning, timing closure, and silicon bring‑up.
• Conduct detailed integration reviews at key customer milestones and resolve complex integration challenges throughout the SoC design flow.
• Document best practices, develop application notes, and deliver training to enable customer success.
• Collaborate with cross‑functional teams to relay customer feedback, contribute to product improvements, and stay current with interface protocols and industry standards.
• Travel occasionally to customer sites for on‑site support, integration reviews, and system bring‑up activities.

Required profile

• Excellent communicator able to engage effectively with customers and cross‑functional teams.
• Organized, detail‑oriented, and capable of managing multiple projects under tight schedules.
• Resourceful problem‑solver who adapts to new challenges and technologies with enthusiasm.
• Customer‑focused, proactive, and collaborative.
• Committed to continuous learning and professional growth.

Required skills

• Deep understanding of ASIC design flows: simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure.
• Hands‑on expertise in RTL and gate‑level simulation debugging.
• Proficiency with front‑end tools such as Design Compiler, Fusion Compiler, and PrimeTime.
• Experience with silicon bring‑up and system‑level characterization in lab environments.
• Domain knowledge of memory subsystems, DDR and LPDDR protocol implementation flows.