Post Silicon Validation Engineer (PHY)

About the role

Cisco Silicon One is looking for a Post Silicon Validation Engineer to join its PHY system group. The team covers the PHY and system aspects of the SerDes communication IP, including PHY firmware, calibrations, system definitions, operations and post-silicon validation, as well as developing the automation infrastructure and tools. The position involves hands-on work in the lab in Caesarea and Netanya.

Key responsibilities

• Work on post-silicon validation of the SerDes communication IP, including PHY firmware, calibrations and system definitions.
• Develop the automation infrastructure and tools used for validation.
• Perform high-speed SerDes characterization, link stability checks and PVT corner testing.
• Debug faults across hardware, software and silicon.

Required profile

• B.Sc or M.Sc in Electrical Engineering, Computer Science or equivalent.
• Experience in PHY/SerDes validation (high-speed SerDes characterization, link stability, PVT corners) and/or other PHY layers of communication systems.
• Proven ability to debug at system level and isolate faults across HW/SW/Silicon.
• Strong scripting and programming skills in Python or C++.
• Practical experience with lab instrumentation such as oscilloscopes, BERTs and spectrum analyzers.

Preferred qualifications

• Knowledge of signal processing and communication theory (DSP, modulation, link-layer communication).
• Linux proficiency, Git and experience with Jenkins or DevOps automation frameworks.
• GUI development experience and database familiarity.
• Understanding of PCIe and Ethernet standards.
• Multi-disciplinary orientation and strong multitasking.