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Logic Designer and FPGA Tech Lead

jj · Yokneam

New
Senior 🇬🇧 English
Verilog SystemVerilog Vivado Quartus Static Timing Analysis SDC constraints Clock-domain crossing PCIe SerDes I2C SPI Artix-7 Kintex UltraScale

Job description

About the role

Johnson & Johnson MedTech is seeking an experienced Logic Designer and FPGA Tech Lead to join its cardiovascular team in Yokneam, Israel. This senior individual‑contributor role provides technical and architectural leadership for FPGA development in advanced electrophysiology medical systems.

Key responsibilities

  • Define and own FPGA architectures and detailed design solutions for complex, real‑time medical systems.
  • Lead end‑to‑end FPGA development from requirements analysis through RTL implementation, integration, verification, hardware bring‑up and delivery.
  • Design, implement and review high‑quality RTL using Verilog and SystemVerilog, translating system requirements and signal‑processing algorithms into efficient FPGA implementations.
  • Drive synthesis, placement, routing, static timing analysis, timing closure, clock‑domain crossing analysis and optimization for performance, power and resource utilization.
  • Lead root‑cause analysis and resolution of FPGA, board‑level and system‑integration issues using simulation and laboratory debugging tools.

Required profile

  • Bachelor’s degree or higher in Electrical or Computer Engineering.
  • At least six years of hands‑on logic design and FPGA/RTL development experience, including leadership of complex FPGA designs.
  • Proven ability to define FPGA architecture and lead development from concept through integration and verification.
  • Experience in a regulated medical‑device environment is an advantage.

Required skills

  • Advanced proficiency in Verilog and SystemVerilog.
  • Hands‑on experience with synthesis and implementation tools such as Vivado and Quartus.
  • Deep understanding of static timing analysis, XDC/SDC constraints, clock‑domain crossing, reset design and low‑skew clocking.
  • Experience with high‑speed interfaces and protocols (PCIe, SerDes, I2C, SPI).
  • Knowledge of signal‑processing algorithm implementation in FPGA.
  • Hardware bring‑up and debugging using oscilloscopes, logic analyzers, protocol analyzers, JTAG and BERT.

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Source : ats:workday

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Published 9 hours ago

Expires 1 month from now

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jj

Yokneam