Senior SOC Clocks RTL Design Engineer

About the role

The NVIDIA System‑On‑Chip (SOC) group is seeking a Senior RTL Design Engineer to lead the development of clocking logic for next‑generation networking chips. This technical‑lead role focuses on RTL implementation of clocks, PLLs, and related infrastructure, guiding the design from specification through silicon bring‑up.

Key responsibilities

• Act as technical lead for SOC clock development, overseeing implementation from specification to tape‑out and bring‑up.
• Collaborate with architecture teams to define clock and reset schemes, gather requirements, and translate them into a verifiable RTL design.
• Write and review synthesizable Verilog/SystemVerilog for clock generation, distribution, muxing, division, glitch‑less switching, gating, and reset synchronization.
• Mentor and review work of other RTL engineers, set coding standards, and allocate tasks.
• Partner with Physical Design on clock‑tree implementation, SDC/timing constraints, floorplan feedback, trial synthesis, and timing convergence.
• Work with Design Verification to create test plans, debug functional and gate‑level issues, and achieve coverage closure.
• Support software/firmware teams on clock programming, DVFS, and low‑power shutdown flows.
• Represent clocking implementation in cross‑functional design reviews with architecture, PD, DV, DFT, and CAD stakeholders.

Required profile

• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of RTL/logic design experience with multiple chips taken to tape‑out.
• Proven technical leadership, including leading a design area, mentoring engineers, and coordinating across teams.
• Strong understanding of how RTL choices impact synthesis, timing, area, and power.

Required skills

• Verilog / SystemVerilog RTL design.
• Clock‑tree synthesis and timing analysis (SDC, timing constraints).
• PLL and clock‑gating design.
• Clock domain crossing, reset synchronization, and glitch‑less switching.
• Physical Design collaboration (floorplan, trial synthesis, timing convergence).
• Design Verification methodologies and test‑plan development.
• DFT and CAD tool interaction.
• Experience with DVFS and low‑power clock‑shutdown flows.