Senior Power Delivery & Integrity Engineer

About the role

Majestic Labs is looking for a highly skilled Senior Power Engineer to lead the definition of board‑level and rack‑level power delivery architecture for next‑generation multi‑kilowatt AI server platforms. The role owns end‑to‑end design of high‑current power paths, voltage conversion strategies, and power‑delivery‑network (PDN) optimization while ensuring compliance with OCP/Open Rack standards.

Key responsibilities

• Architect board‑level, server‑level, and rack‑level power delivery systems for high‑power subsystems.
• Define PDN topology, select components (VRMs, FETs, inductors, caps, connectors, busbars) and create derating, margin, and reliability guidelines.
• Lead decoupling capacitor strategy across package and PCB layers to meet target impedance and transient response goals.
• Drive power‑integrity analysis (AC/DC, Z‑target, transient, EMI/EMC) and validate designs through modeling, simulation, and lab measurement.
• Collaborate with mechanical, thermal, silicon, and systems engineers to align high‑current routing, cooling requirements, and system constraints.

Required profile

• BS/MS in Electrical Engineering or related field.
• 10+ years of experience in high‑power delivery design for SoCs.
• Deep expertise in power‑integrity, PDN modeling, VRM design, and transient response optimization.
• Strong communication and cross‑functional collaboration skills.

Required skills

• Proficiency with SPICE and PDN simulation tools (Keysight, Cadence Sigrity/Clarity, Ansys SIwave).
• Experience using measurement equipment such as VNAs, oscilloscopes, and electronic loads.
• Power‑integrity analysis, EMI/EMC mitigation, and high‑current PCB design.
• Knowledge of OCP/Open Rack power distribution standards and rack‑level power architectures.