Junior Verification Engineer

About the role

We are seeking talented, self‑motivated engineers to join our Design Verification (DV) team in a junior or mid‑level position. The team works on some of the most technically challenging silicon, covering digital and analog design, DSP pipelines, and firmware‑hardware co‑verification.

Key responsibilities

• Perform constrained‑random and coverage‑driven verification of complex high‑speed SerDes mixed‑signal IP.
• Validate DSP datapaths and conduct joint firmware/hardware verification.
• Develop and maintain advanced verification environments.
• Leverage AI‑assisted tools as part of the daily engineering workflow.

Required profile

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with a strong academic record.
• Solid understanding of digital design, computer architecture, and software programming.
• Analytical mindset with a passion for root‑causing problems.
• Ability to thrive in a dynamic, multi‑disciplinary environment.
• Hands‑on exposure to SystemVerilog/UVM or Python is a significant advantage.

Required skills

• SystemVerilog
• UVM methodology
• Python scripting for verification automation
• Mixed‑signal or analog simulation concepts
• High‑speed protocols such as PCIe and Ethernet
• DSP verification techniques
• AI‑assisted verification tools

What we offer

• A collaborative and innovative environment where ideas come from every level.
• Exposure to the full verification lifecycle from specification to tape‑out sign‑off.
• A culture that embraces modern tooling, including AI‑assisted engineering.
• Clear growth path from day one.
• A supportive team that values each other's success.