Senior Hardware Verification Engineer (UVM)

About the role

Renesas Electronics is hiring a full-time, on-site Senior Hardware Verification Engineer based in Raanana, Israel. The role centres on developing and maintaining UVM-based verification environments for complex IP and SoC designs, working closely with design, architecture and firmware teams.

Key responsibilities

• Analyze specifications, define verification plans and create and run verification scenarios
• Write testbenches, test cases and coverage models, and debug RTL issues
• Run regressions, monitor coverage metrics and perform root-cause analysis of failures
• Contribute to improving verification methodologies and automation
• Mentor junior engineers, take part in design and verification reviews and align verification with project schedules and quality standards

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field
• Background in electrical engineering or a related field, able to interpret circuit-level and system-level specifications
• Effective communication and collaboration skills in cross-functional, multicultural teams
• Experience in semiconductor product development for automotive, industrial or embedded systems is an advantage

Required skills

• Hardware verification with UVM methodology and constrained-random verification
• Formal verification techniques and tools
• RTL design with Verilog/SystemVerilog, synthesis considerations and DFT best practices
• Proficiency with simulators, waveform viewers, coverage tools, regression management and scripting in Python/Perl/Tcl