Senior ASIC Verification Engineer – Security & RISC‑V

About the role

NVIDIA is building a new group in Israel focused on security engines and RISC‑V processor IPs. As a Senior ASIC Verification Engineer you will lead verification efforts for high‑performance, low‑power security modules and RISC‑V cores, collaborating with architects, designers, and software teams.

Key responsibilities

• Participate in micro‑architecture development and write detailed specifications.
• Design and implement SystemVerilog UVM verification environments for crypto and RISC‑V IP blocks.
• Create verification and test plans to achieve full coverage.
• Debug and resolve bugs in partnership with design engineers.
• Deliver verified IPs to higher‑level verification stages such as cluster, full‑chip and emulation.

Required profile

• Bachelor’s degree in Electrical or Computer Engineering.
• 5+ years of experience verifying complex ASIC designs.
• Strong interpersonal skills and ability to work in a global, multi‑cultural team.

Required skills

• SystemVerilog
• UVM methodology
• Experience with crypto RTL units (AES, RSA, PQC)
• RISC‑V architecture or peripheral verification

What we offer

• Competitive salary and generous benefits package.
• Opportunity to work on cutting‑edge technology used in AI, graphics, and autonomous vehicles.
• Collaborative environment with top talent worldwide.