RTL Design Engineer (ASIC) - Tel Aviv Office

About the role

Micron Technology is looking for an RTL design engineer to develop digital blocks from specification through RTL implementation, with a strong emphasis on power-efficient, implementation-aware design. The role works hands-on with synthesis and timing/power analysis tools to balance power, performance and area, and collaborates with multi-functional teams to improve the quality of advanced flash memory products. The position is based in the Tel Aviv office.

Key responsibilities

• Develop and implement RTL for digital and mixed-signal blocks using System Verilog.
• Perform front-end quality checks including lint, CDC/RDC, synthesis, UPF and timing QoR.
• Design power- and area-efficient RTL, reducing switching activity, clock power and leakage.
• Complete RTL- and gate-level power and timing evaluation to identify and resolve PPA bottlenecks.
• Work with verification, synthesis and physical design teams to achieve timing closure and design targets.

Required profile

• Bachelor's degree with 4+ years of pre-silicon RTL design experience, or a Master's degree in Electrical Engineering with demonstrated ability.
• Experience developing RTL for complex digital IP from specification through implementation handoff.
• Hands-on experience with ASIC low-power methodologies, including UPF-based power intent and CDC/RDC analysis.
• Strong understanding of ASIC front-end flows (RTL design, synthesis, static timing analysis).
• Proficiency in Verilog/SystemVerilog and industry-standard simulation tools.

Preferred qualifications

• RTL and gate-level power analysis with tools such as Design Compiler and PrimeTime.
• Low-power techniques such as clock gating, power gating and multi-voltage designs.
• Cross-team collaboration across RTL, verification, synthesis/STA and physical design.
• Familiarity with CMOS digital and mixed-signal circuit concepts.
• Memory or high-performance digital build experience.