Senior Design Engineer

About the role

Marvell is seeking a Senior Design Engineer to lead the development of digital blocks for next‑generation network switches. You will be part of a highly skilled team responsible for defining architecture, designing, and verifying IP cores that power enterprise, cloud, AI, and carrier solutions.

Key responsibilities

• Own one or more key digital blocks, driving design from architecture definition through implementation.
• Optimize area, timing, lint, and CDC/RDC aspects of the block.
• Collaborate closely with verification engineers to support block‑level verification and ensure design‑verification alignment.

Required profile

• Electrical Engineering B.Sc. or M.Sc. degree.
• 5+ years of experience in digital design.
• Proficiency in RTL design using Verilog or SystemVerilog.
• Experience with linting, CDC/RDC analysis, synthesis, timing closure, power optimization, and backend flows.
• Verification experience with SystemVerilog and UVM is a plus.
• Strong analytical, problem‑solving, and communication skills.

Required skills

• Verilog
• SystemVerilog
• RTL design
• Linting
• CDC/RDC analysis
• Synthesis
• Timing closure
• Power optimization
• Backend flow knowledge
• UVM (advantage)

What we offer

• Competitive compensation and comprehensive benefits.
• Collaborative, transparent, and inclusive work environment.
• Opportunities for growth and development on impactful semiconductor projects.