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ASIC Chief Architect

Ethosia · Hod Hasharon

Senior 🇬🇧 English
DSP architectures signal-processing systems parallel processing hardware accelerators heterogeneous computing DDR4 DDR5 LPDDR HBM memory controllers cache architectures packet processing networking systems network processors switching routing traffic management PCIe Ethernet CXL UCIe high-speed interfaces NoC chiplet architectures power management performance optimization system modeling architectural simulations performance analysis workload characterization HW/SW co-optimization ASIC design flows silicon bring-up wireless communications modem AI datacenter silicon

وصف الوظيفة

About the role

We are seeking an ASIC Chief Architect to lead the definition and implementation of next‑generation silicon products. You will shape the architectural vision from concept through silicon bring‑up, driving high‑performance SoC designs for demanding applications.

Key responsibilities

  • Define and own the overall ASIC/SoC architecture, including CPU, DSP, GPU, and accelerator blocks.
  • Lead cross‑functional teams through architecture, simulation, verification, and silicon bring‑up.
  • Optimize power, performance, and area across memory subsystems, high‑speed interfaces, and chiplet integrations.
  • Collaborate with system modeling, workload characterization, and HW/SW co‑optimization groups.
  • Mentor senior architects and technical leaders, fostering innovation and best practices.

Required profile

  • MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 12+ years of experience in semiconductor, ASIC, SoC, or processor architecture.
  • Proven track record delivering complex, high‑volume commercial ASICs.
  • Strong publication or patent record and ability to communicate architectural vision to executives.

Required skills

  • DSP architectures and signal‑processing systems
  • CPU architectures (ARM, RISC‑V, x86)
  • GPU and parallel processing architectures
  • Hardware accelerators and heterogeneous computing
  • DDR4, DDR5, LPDDR, HBM, memory controllers, cache architectures
  • Packet processing, networking systems, network processors, switching, routing, traffic management
  • PCIe, Ethernet, CXL, UCIe and other high‑speed interfaces
  • NoC and chiplet architectures
  • Power management and performance optimization
  • System modeling, architectural simulations, performance analysis, workload characterization
  • HW/SW co‑optimization, ASIC design flows, silicon bring‑up
  • Experience with wireless communications, modem, AI, or datacenter silicon

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Ethosia

Hod Hasharon