Senior VLSI Integration Engineer

About the role

The NVIDIA System‑On‑Chip (SoC) group is seeking a Senior VLSI Integration Engineer to drive chip‑level design and integration for high‑performance networking chips. You will collaborate with cross‑functional teams to deliver robust ASIC solutions while focusing on automation, quality, and efficiency.

Key responsibilities

• Implement chip‑level design in partnership with Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design teams.
• Address functional and structural challenges such as functional debug, physical design readiness, emulation, and design‑quality issue resolution.
• Perform daily chip design tasks including partitioning, CDC, RDC, trial synthesis, and design‑quality checks.
• Contribute to the development and deployment of design flows.

Required profile

• B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering.
• 7+ years of hands‑on experience in ASIC/chip design.
• Strong RTL design expertise in SystemVerilog.
• Proficiency in at least one scripting language (Python, Bash, or Tcl).
• Ability to work effectively within multidisciplinary teams.

Required skills

• SystemVerilog
• Python
• Bash
• Tcl
• RTL design
• Chip design
• Clock domain crossing (CDC)
• Reset domain crossing (RDC)
• Trial synthesis
• Design quality checks

What we offer

• Opportunity to work on cutting‑edge networking chips.
• Collaboration with leading experts in ASIC, physical design, CAD, package design, software, and DFT.
• Exposure to advanced automation and methodology development.