Senior Staff Engineer – Memory IP Applications

About the role

Synopsys is seeking a Senior Staff Engineer to lead the integration of Memory Sub System IPs into ASIC and SoC designs. The role combines hands‑on technical support, customer interaction, and cross‑functional collaboration to ensure successful deployment of high‑performance memory interfaces.

Key responsibilities

• Provide technical guidance and hands‑on support to customers integrating Synopsys Memory Sub System IPs into ASIC/SoC designs, and conduct detailed integration reviews at key milestones.
• Troubleshoot complex integration challenges across the SoC design flow, including RTL simulation, synthesis, floorplanning, timing closure, and silicon/system bring‑up.
• Support silicon bring‑up and characterization in system environments to ensure successful deployment of Synopsys IP.
• Document best practices, develop application notes, and deliver training to enable customer success with Synopsys solutions.
• Participate in cross‑functional teams to relay customer feedback, contribute to product improvements, and stay current with interface protocols and industry standards.
• Occasionally travel to customer sites for on‑site support, integration reviews, and system bring‑up activities.

Required profile

• Excellent communicator able to engage effectively with customers and cross‑functional teams.
• Organized and detail‑oriented with a track record of meeting tight schedules and managing multiple projects.
• Resourceful problem‑solver who adapts to new challenges and technologies with enthusiasm.
• Customer‑focused, proactive, and collaborative in approach.
• Committed to continuous learning and professional growth.

Required skills

• Strong understanding of ASIC design flows: simulation, verification, RTL synthesis, floorplanning, physical design, and timing closure.
• Hands‑on expertise integrating and validating high‑speed memory subsystem IPs (DDR, LPDDR).
• Proficiency in RTL and gate‑level simulation debugging.
• Familiarity with Design Compiler, Fusion Compiler, and PrimeTime tools.
• Experience with silicon bring‑up and system‑level characterization in lab environments.
• Knowledge of DDR and LPDDR protocols and implementation flows.