Senior CPU Design Verification Engineer

About the role

Join a research and development team that creates custom silicon solutions for Google Cloud products. You will work on verification of digital designs, building constrained‑random environments and driving verification closure for next‑generation hardware.

Key responsibilities

• Plan verification of digital blocks by understanding specifications and collaborating with design engineers.
• Create and enhance constrained‑random verification environments using SystemVerilog and UVM, or apply formal verification with SystemVerilog Assertions and industry‑leading tools.
• Define and implement coverage measures to expose corner‑case bugs and track progress toward tape‑out.
• Debug test failures with design engineers to ensure functional correctness.
• Close coverage gaps and deliver comprehensive verification reports.

Required profile

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• At least 8 years of experience creating and using verification components in standard methodologies.
• Hands‑on experience verifying RTL designs for FPGAs or ASICs using SystemVerilog or Specman/E.
• Advanced degree (Master's or PhD) and additional 3 years of verification experience are preferred.
• Knowledge of CPU/processor architectures (ARM, x86, RISC‑V) and ASIC standard interfaces is highly beneficial.

Required skills

• SystemVerilog
• Specman/E
• UVM (Universal Verification Methodology)
• SystemVerilog Assertions (SVA) and formal verification tools
• Constrained‑random verification
• Coverage analysis and closure
• ASIC verification flow
• Understanding of CPU architecture, pipelines, caches, and memory subsystems