Principal Architect – High‑Performance Connectivity

About the role

We are seeking an experienced Principal Architect to lead the architecture of high‑performance connectivity solutions, focusing on PCIe, high‑speed networking, and Ethernet‑based systems. The role will define next‑generation architectures for AI infrastructure at the intersection of silicon, system, and protocol design, enabling hyperscale customers to build scalable, high‑bandwidth, low‑latency systems.

Key responsibilities

• Define and drive system‑level and chip‑level architecture for high‑speed connectivity products.
• Lead architecture for PCIe‑based interconnects, networking protocols, and Ethernet subsystems.
• Analyze system requirements and translate them into scalable, efficient hardware architectures.
• Perform trade‑off analysis across performance, power, latency, area, and cost.
• Collaborate with RTL, physical design, firmware, validation, and product engineering teams.
• Define and review micro‑architecture specifications and ensure cross‑team alignment.
• Support performance modeling, simulation, and architectural validation.
• Engage with customers and partners to capture emerging use cases and requirements.

Required profile

• 10+ years of experience in semiconductor architecture, ASIC design, or system engineering.
• Strong expertise in PCIe architecture (Gen4/5/6+) and its ecosystem.
• Deep understanding of networking and Ethernet standards (25G/50G/100G/400G and beyond).
• Experience designing high‑speed, low‑latency data paths and integrating SerDes‑based PHYs.
• Proven ability to drive architecture from concept to silicon.

Required skills

• PCIe (Gen4/5/6+)
• Ethernet (25G/50G/100G/400G)
• CXL, NVLink, UALink protocols
• SerDes and high‑speed PHY integration
• Networking stacks, switching, RDMA
• Performance modeling tools and architectural simulators
• Power and performance optimization techniques at system level
• ASIC design and SoC integration