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ASIC Leader - Verification

cisco · Tel Aviv-Yafo

New
Senior 🇬🇧 English
UVM Functional verification MATLAB GLS Mixed-signal

Job description

About the role

Cisco Silicon One, the front-end design team behind Cisco's silicon development, is looking for an ASIC Leader. The team covers the full chip design spectrum, from definition and architecture through RTL design, verification, signoff and validation, using advanced silicon technologies to build large-scale, advanced devices.

Key responsibilities

  • Review micro-architecture specifications
  • Supervise verification team members and provide professional guidance
  • Implement a UVM-based verification environment
  • Collaborate with design engineers to resolve bugs and achieve coverage closure
  • Work with firmware and lab teams to verify chip flows
  • Perform debug, root-cause analysis and post-silicon validation in the lab

Required profile

  • B.Sc. or M.Sc. in Electrical Engineering from a top university
  • 10+ years of experience in the field

Required skills

  • Knowledge of UVM and functional verification methodologies
  • Preferred: experience with MATLAB simulations and bit-exact modeling environments
  • Preferred: familiarity with mixed-signal systems and environments
  • Preferred: knowledge and hands-on experience with GLS

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Source : ats:workday

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Published 2 hours ago

Expires 1 month from now

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cisco

Tel Aviv-Yafo