SoC Chip Architect – High‑Performance Custom Silicon

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct‑to‑consumer products. You’ll contribute to the innovation behind products loved by millions worldwide, shaping the next generation of hardware experiences with unparalleled performance, efficiency, and integration.

Key responsibilities

• Lead top‑level SoC architecture across IP, digital design, verification, physical design, validation, firmware, power management, security, and system software.
• Architect and analyze complex multi‑chiplet systems, including chip partitioning, die‑to‑die interconnects, advanced packaging constraints, and high‑performance on‑chip fabrics (NoC).
• Define SoC subsystems, memory hierarchies, clock distribution, reset schemes, and power domains to ensure optimal performance and efficiency.
• Formulate operational flows, latency models, and throughput analyses for data‑center AI workloads.
• Own the SoC architecture specification throughout concept, modeling, implementation, tape‑out, and post‑silicon bring‑up.

Required profile

• Bachelor’s degree in Electrical or Computer Engineering (or equivalent practical experience).
• 15 years of experience leading architectural definition of high‑performance SoCs, ASICs, or multi‑chiplet systems from concept through production.
• Experience working across hardware, firmware, and system‑software boundaries with system‑level reasoning.
• Master’s or PhD in Electrical/Computer Engineering (preferred).
• Experience with AI workload analysis, mapping across data‑center components, and optimizing hardware solutions for AI.

Required skills

• SoC interconnect and memory‑hierarchy design.
• Multi‑chiplet system architecture, advanced 2.5D/3D packaging, D2D interfaces such as UCIe, BoW, high‑speed SerDes.
• System‑level fabric (NoC) development.
• Hardware‑firmware‑software integration and power‑management domain design.
• High‑performance AI accelerator and compute chiplet optimization.