Senior SoC and IP Design Engineer

About the role

Join Google Cloud's AI and Infrastructure team as a Senior SoC and IP Design Engineer. You will develop custom silicon solutions that power Google’s direct‑to‑consumer products, delivering high performance, efficiency, and integration for millions of users worldwide.

Key responsibilities

• Define block‑level design documentation, including interface protocols, block diagrams, transaction flows, and pipelines.
• Write and debug RTL code in Verilog/SystemVerilog, perform functional and performance simulations, and run Lint/CDC/FV/UPF checks.
• Participate in synthesis, timing, and power‑closure activities to meet design targets.
• Develop test plans, conduct coverage analysis, and support SoC‑level verification.
• Collaborate with multi‑disciplinary, multi‑site teams to ensure successful design sign‑off.

Required profile

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent practical experience).
• At least 8 years of experience in digital logic design, RTL coding, and low‑power design techniques.
• Proven experience with design sign‑off and quality tools such as Lint and CDC.
• Experience in SoC or IP architecture design.
• Preferred: Master’s or PhD and knowledge of high‑performance/low‑power design, formal verification, FPGA/emulation platforms, and DDR/LPDDR/HBM technologies.

Required skills

• Verilog and SystemVerilog
• RTL design and coding
• Logic synthesis and optimization
• Low‑power design techniques
• Design sign‑off tools (Lint, CDC, formal verification)
• SoC/IP architecture
• FPGA and emulation platforms
• DDR, LPDDR, and High‑Bandwidth Memory (HBM) knowledge