Senior Chip Architect – NIC & DPU

About the role

We are seeking a Senior Chip Architect to join NVIDIA’s networking unit, focusing on the next‑generation NIC and DPU products. As part of a small elite team, you will shape the architecture, collaborate across hardware and software groups, and tackle complex full‑chip challenges.

Key responsibilities

• Deeply understand and document NIC architecture, serving as a knowledge hub for design and verification engineers.
• Define and drive the architecture of upcoming NVIDIA NIC and DPU systems, coordinating with GPU and CPU teams.
• Balance architectural requirements with backend, execution, and design constraints for sophisticated product features.
• Specify product‑on‑release (POR) requirements and address full‑chip correctness and performance issues.
• Collaborate with board and package teams to address power, di/dt, temperature, and signal‑integrity limits.
• Maintain expertise in SoC flows, PCIe, Ethernet, InfiniBand, and NvLink protocols.

Required profile

• B.Sc. or M.Sc. in Electrical Engineering from a recognized university with excellent grades.
• 5+ years of experience in ASIC design, micro‑architecture, or performance engineering.
• At least 4 years of hands‑on Verilog or VHDL development.
• Strong analytical and debugging abilities, with proven capability to lead cross‑functional activities.
• Excellent communication skills.

Required skills

• Verilog
• VHDL
• ASIC design
• Micro‑architecture development
• Performance analysis and debugging
• SoC flow knowledge
• PCIe protocol
• Ethernet
• InfiniBand
• NvLink