Micro-Architect, Networking (Google Cloud)

About the role

Google’s AI and Infrastructure team is looking for a Micro‑Architect to lead the design of high‑performance networking ASICs that power Google Cloud services. You will work on custom silicon that enables low‑latency, high‑throughput, and secure data movement for billions of users worldwide.

Key responsibilities

• Lead design activities for IP blocks, subsystems and full SoCs, defining block‑level specifications, interfaces, and transaction flows.
• Develop and debug RTL in Verilog, SystemVerilog or VHDL, and perform functional and performance simulations.
• Run synthesis, timing, power analysis and support FPGA/silicon bring‑up.
• Create test plans, coverage analysis and verification strategies for block and SOC‑level validation.
• Collaborate with software teams to optimise hardware/software interfaces and ensure seamless integration.

Required profile

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent practical experience.
• At least 8 years of experience designing networking ASICs from specification to production.
• Minimum 4 years of technical leadership experience.
• Proven experience in micro‑architecture, RTL design, verification, logic synthesis, timing closure and power optimisation.

Required skills

• RTL coding in Verilog, SystemVerilog, VHDL.
• Micro‑architecture, design verification, logic synthesis, timing and power analysis.
• Procedural programming: C++, Python, Go.
• Knowledge of TCP/IP, Ethernet, PCIe and DRAM protocols.
• Familiarity with Network‑on‑Chip (NoC) principles and protocols such as AXI, ACE, CHI.

What we offer

• Opportunity to work on cutting‑edge silicon that powers Google’s global services.
• Collaborative environment with top‑tier hardware and software engineers.
• Flexible location choice between Tel Aviv and Haifa.