Logic Design Engineer

About the role

Cisco Silicon One Front-End Design team is looking for a Logic Design Engineer. The team covers the full spectrum of chip design, from definition and architecture through RTL design, verification, signoff and validation, using advanced silicon technologies to develop large-scale devices. The role sits within the Silicon One programmable architecture that powers Cisco's routing portfolio.

Key responsibilities

• Write and review micro-architecture specifications
• Implement RTL (Verilog/SystemVerilog) to meet timing, performance and power requirements
• Contribute to full chip integration, timing methodology and analysis
• Collaborate with verification engineers to resolve bugs and achieve coverage closure
• Work with the physical design team to close timing and PnR issues
• Support design methodology evolution and best practices
• Perform debug, root-cause analysis and post-silicon validation in the lab

Required profile

• B.Sc. or M.Sc. in Electrical Engineering from a top university
• 6+ years of experience in a relevant field
• RTL design experience

Required skills

• Familiarity with UVM and functional verification methodologies
• Preferred: experience with MATLAB simulations and bit-exact modeling environments
• Preferred: familiarity with mixed-signal systems and environments
• Preferred: knowledge and hands-on experience with Clock Domain Crossing (CDC)