Junior Physical Design Engineer

About the role

Join a fast‑moving Physical Design team that owns end‑to‑end chip development, from definition through tape‑out. As a Junior Physical Design Engineer you will be responsible for turning RTL into a tape‑out‑ready GDS layout while collaborating closely with Design, Architecture, and Front‑End teams.

Key responsibilities

• Own a physical‑design block from RTL to final GDS, ensuring full sign‑off.
• Lead floorplan exploration in partnership with Front‑End and Architecture groups.
• Partner on static timing analysis (STA) to manage block and top‑level constraints.
• Conduct synthesis exploration, deliver netlists, and perform scan insertion, UPF integration, and lint/Spyglass checks.
• Drive the place‑and‑route flow, optimizing power, performance, and area (PPA).
• Perform sign‑off activities across STA, IR/EM, physical verification, logic equivalence checking, and low‑power verification.

Required profile

• BSc or MSc in Computer Engineering or Electrical Engineering.
• 0–2 years of industry experience.
• Proficiency in scripting languages such as Tcl, Python, Perl, or tcsh.
• Strong teamwork and communication skills with a proactive, “can‑do” attitude.

Required skills

• Tcl
• Python
• Perl
• tcsh
• Static timing analysis (STA)
• Synthesis flow and netlist generation
• Scan insertion and UPF handling
• Lint/Spyglass verification
• Place‑and‑route flow
• Physical verification and low‑power verification