Experienced PCIe System Design Engineer

About the role

Sandisk is seeking a hands‑on System Engineer to lead the design, implementation, and silicon validation of PCIe interfaces within its System‑on‑Chip (SoC) products. The role focuses on high‑speed connectivity, NVMe compatibility, and bringing up PCIe links on silicon.

Key responsibilities

• Define and implement PCIe controller and PHY IP, including configuration for Gen 4/5 (Gen 6 a plus).
• Develop protocol logic such as DOE, IDE, and MFND/SR‑IOV features.
• Integrate PCIe/PHY IP into the SoC fabric and create Control and Status Registers (CSRs) for hardware‑firmware interaction.
• Design power‑management mechanisms (ASPM, L1 Substates) and system‑level reset sequences.
• Perform PCIe link bring‑up, connectivity testing, and data‑path optimization on silicon.
• Troubleshoot complex multi‑discipline issues using AI‑driven debug tools, protocol analyzers, and high‑speed oscilloscopes.

Required profile

• 7+ years of experience as a System/Design/Validation Engineer with a focus on PCIe.
• Deep expertise in PCIe Gen 4/5 standards; knowledge of Gen 6 is a strong advantage.
• Solid understanding of the NVMe protocol, including queue management and command sets.
• Hands‑on experience with PCIe protocol analyzers and high‑speed oscilloscopes.
• Proficiency in Python and C for test automation and hardware debugging.
• B.Sc. in Electrical Engineering or Computer Engineering from a recognized institution.
• Ability to collaborate across multidisciplinary teams.

Required skills

• PCIe Gen 4
• PCIe Gen 5
• PCIe Gen 6 (optional)
• NVMe protocol
• Python programming
• C programming
• Test automation
• Hardware debugging
• High‑speed oscilloscopes
• PCIe protocol analyzers