Digital IC Design Intern – Chip Power Estimation

About the role

Marvell's Power Design team drives power efficiency across the chip design lifecycle, from early architecture and RTL through physical implementation and signoff. The team owns the methodologies, tools and flows used to estimate, analyze, track and optimize chip power, working with architecture, RTL, verification and physical design teams to balance power, performance and area. This internship lets you join the team and ramp up on chip power estimation.

Key responsibilities

• Ramp up on chip power estimation methodologies, tools and power calculators.
• Perform power analysis and identify optimization opportunities throughout the chip design lifecycle.
• Explore and implement power optimizations at RTL and physical design levels.
• Develop automation and improve existing power analysis and estimation flows.
• Explore the use of AI tools for power analysis, optimization and design-flow automation.
• Analyze power trends and identify high-impact areas for improvement.
• Collaborate with RTL, physical design, architecture and power teams, and gradually become a power focal point within the team.

Required profile

• At least 2nd-year student in Electrical Engineering, Computer Engineering, Computer Science or a similar field.
• Coursework covering foundational principles of circuit design, circuit theory, digital logic design or electronics.
• Team player willing to share knowledge and present work and lessons learned in a short PowerPoint summary.

The position may require access to technology and software subject to U.S. export control laws, so applicants must be eligible to access export-controlled information. Candidates are not allowed to use AI tools during interviews.