ASIC Design Engineer – Tel Aviv Office

About the role

Micron Technology is seeking an ASIC Design Engineer to develop digital and mixed‑signal blocks for advanced flash memory products. The position is based in the Tel‑Aviv office (ToHa Building, near HaShalom train station) and focuses on power‑efficient RTL implementation.

Key responsibilities

• Develop and implement RTL for digital and mixed‑signal blocks using SystemVerilog.
• Perform front‑end quality checks such as lint, CDC/RDC, synthesis, UPF, and timing QoR.
• Design power‑ and area‑efficient RTL, reducing switching activity, clock power, and leakage.
• Complete RTL‑ and gate‑level power and timing evaluation to resolve PPA bottlenecks.
• Collaborate with verification, synthesis, and physical design teams to achieve timing closure and design targets.

Required profile

• Bachelor’s degree with 4+ years of pre‑silicon RTL design experience or a Master’s degree in Electrical Engineering.
• Experience developing RTL for complex digital IP from specification through implementation handoff.
• Hands‑on experience with ASIC low‑power methodologies, including UPF‑based power intent and CDC/RDC analysis.
• Strong understanding of ASIC front‑end flows: RTL design, synthesis, and static timing analysis.

Required skills

• SystemVerilog / Verilog.
• ASIC low‑power methodologies (UPF, clock gating, power gating, multi‑voltage).
• Front‑end tools: Design Compiler, PrimeTime.
• Power and timing analysis at RTL and gate level.