ASIC Design Engineer

About the role

You will work on developing the next generation of Mobileye System‑on‑Chip for ADAS and autonomous vehicles. The position requires deep understanding of micro‑architecture, designing proprietary IPs and integrating third‑party IPs in a multi‑clock domain environment.

Key responsibilities

• Develop the next‑generation Mobileye SoC for ADAS and autonomous driving.
• Design and implement new proprietary IP blocks and system features.
• Integrate third‑party and proprietary IPs across multiple clock domains.
• Perform verification, synthesis, static timing analysis and closure.
• Optimize power consumption and silicon area.
• Become proficient with the design flow, tools, and methodologies.
• Collaborate with product definition, verification, software and physical design teams.

Required profile

• B.Sc. in Electrical Engineering or Computer Engineering.
• 1‑3 years of ASIC/FPGA design experience.
• Familiarity with simulation environments and verification methodologies.
• Experience with a full design cycle: RTL, verification, synthesis, timing closure, CDC and lint.
• Scripting experience in Python, Perl or TCL is a plus.

Required skills

• ASIC and FPGA design.
• RTL coding and verification.
• Synthesis and static timing analysis.
• Power and area optimization.
• Multi‑clock domain integration.
• Python, Perl, TCL scripting.