ASIC Design Engineer

About the role

Mobileye’s EyeQ VLSI team is seeking an ASIC Design Engineer to contribute to the development of next‑generation SoCs for advanced driver‑assistance systems (ADAS) and autonomous vehicles. The role involves working on cutting‑edge technology to deliver high‑performance, low‑power chips that power Mobileye’s EyeQ family.

Key responsibilities

• Design and implement proprietary IP blocks and system features for future EyeQ SoCs.
• Integrate third‑party and in‑house IPs within multi‑clock domain architectures.
• Perform verification, synthesis, static timing analysis, and drive closure activities.
• Optimize power consumption and silicon area throughout the design flow.
• Collaborate with product definition, verification, software, and physical design teams.
• Become proficient with the design environment, tools, methodologies, and optimization techniques.

Required profile

• B.Sc. in Electrical Engineering, Computer Engineering or a related field.
• 1–3 years of experience in ASIC or FPGA design.
• Hands‑on experience with a full design cycle including RTL coding, verification, synthesis, timing closure, CDC and lint checks.
• Strong teamwork and communication skills with an entrepreneurial, self‑motivated attitude.

Required skills

• RTL design and verification.
• Synthesis and static timing analysis.
• Clock domain crossing (CDC) and linting.
• Power and area optimization.
• Scripting in Python, Perl and TCL.