Senior ASIC DFT Engineer

About the role

Intel is building a new team from scratch in Haifa to develop hardware for AI workloads, with a startup-like culture and short feedback loops. This is a senior, hands-on role with broad technical influence: you will own central DFT aspects of a new family of chips, defining their architecture, planning and implementation, and help shape the team's methodologies and workflows.

Key responsibilities

• Define DFT architecture and strategy for complex AI acceleration IPs and subsystems, balancing test coverage, area, timing and power.
• Build the DFT implementation (scan, compression, boundary scan/JTAG, MBIST, test access and control) and drive fault coverage closure to sign-off.
• Lead ATPG and pattern generation.
• Contribute to DFT methodologies and working flows, and champion the adoption of AI tools across the DFT flow.
• Collaborate with design, verification, physical design and product/test engineering teams, supporting silicon bring-up, debug and yield/quality analysis.

Required profile

• B.Sc. in Electrical Engineering, Computer Engineering or equivalent.
• 6+ years of hands-on DFT experience, driving DFT solutions from architecture through silicon bring-up.
• Demonstrated ownership of complex DFT solutions and ability to drive technical decisions across cross-functional teams.

Required skills

• Deep knowledge of scan insertion, compression, ATPG, JTAG and MBIST.
• Strong intuition for AI tools and interest in applying them to the DFT flow.
• Advantage: experience on large, high-performance or AI/ML accelerator designs, hierarchical DFT, low-power test, in-system test or silicon debug/bring-up.

The role is eligible for a hybrid work model, splitting time between the site and off-site. Shift 1 (Israel).