Physical Design & PPA Optimization Engineer

About the role

Intel's team optimizes its process technology to meet the needs of next-generation silicon designs, partnering with Core and SoC design teams worldwide to deliver high-performance, low-power products. As a Physical Design & PPA Optimization Engineer, you will help achieve best-in-class Power, Performance and Area (PPA) for Intel IPs, evaluating new process technologies and turning findings into actionable recommendations.

Key responsibilities

• Define and run DTCO experiments to evaluate the interaction between process technology and physical design implementation.
• Develop design optimization methodologies across physical design flow domains such as placement, CTS, routing and timing closure.
• Run the full PnR flow to evaluate new technology impacts on PPA metrics.
• Identify trade-offs and optimization opportunities at the device, cell and block level.

Required profile

• BSc or MSc in Electrical Engineering, Computer Engineering or a related field.
• Hands-on experience in physical or circuit design.
• Preferred: 2+ years of experience in physical design or circuit design.
• Preferred: familiarity with physical design implementation flows and methodologies, and experience developing physical design methodologies and analysis tools.

Required skills

• Basic scripting with Python, Tcl or a similar language.
• Strong analytical and problem-solving skills.
• Ability to analyze implementation results and communicate conclusions clearly.

The role is based in Haifa, Israel, and is eligible for a hybrid work model. It is posted as an experienced hire.