Networking Silicon Architect – Cloud

About the role

In this role you will shape the future of AI/ML hardware acceleration by driving Google’s cutting‑edge Tensor Processing Unit (TPU) technology. You will design and verify custom silicon that powers high‑performance networking accelerators and interconnects for Google data centers. The position combines system‑level architecture, ASIC design, and close collaboration with software and hardware teams.

Key responsibilities

• Evaluate silicon solutions for Google’s data‑center networking roadmap, including off‑the‑shelf components, vendor co‑developments and custom designs.
• Design high‑performance hardware/software interfaces and define performance test plans.
• Collaborate with system, software, verification, physical design, packaging and silicon validation stakeholders to ensure complete and performant designs.
• Drive vendor execution for standard component roadmaps, build‑to‑spec projects and co‑development engagements.
• Contribute to the evaluation of future ASIC architectures and overall networking infrastructure.

Required profile

• Bachelor’s degree or equivalent practical experience.
• At least 15 years of experience architecting networking ASICs from specification to production.
• Proven expertise in low‑latency, high‑throughput, secure and reliable network architecture.
• Strong background in RTL development, micro‑architecture, verification, logic synthesis and timing closure.

Required skills

• TCP/IP and Ethernet protocols
• Python and shell scripting
• RTL development for ASIC subsystems
• Micro‑architecture design and verification
• Logic synthesis and timing closure
• Packet classification, queueing, scheduling, switching and routing
• Traffic conditioning and telemetry
• Large‑scale ASIC and SoC architecture
• Performance analysis, modeling and network simulation