Digital IC Design Intern - ATPG Engineer

About the role

Marvell is seeking a motivated and detail-oriented student to join its Design-for-Test (DFT) team as an ATPG (Automatic Test Pattern Generation) Engineer in Yokneam. The role offers hands-on experience developing and implementing test methodologies for complex SoC designs, covering scan insertion, pattern generation and fault coverage analysis.

Key responsibilities

• Assist in setting up the scan insertion and ATPG flow for digital designs.
• Generate and validate test patterns for stuck-at and transition faults.
• Analyze fault coverage and identify areas for improvement.
• Support silicon bring-up and debug of test-related issues.
• Collaborate with design, DV, validation and SW teams to meet testability requirements.
• Document methodologies, results and best practices.

Required profile

• 2nd or 3rd year student with a B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering or a related field.
• Strong analytical and problem-solving skills.
• Excellent communication and teamwork abilities.

Required skills

• Basic understanding of digital logic design and VLSI concepts.
• Familiarity with scripting languages such as Python, Perl or TCL.
• Exposure to EDA tools such as Synopsys TetraMAX or Cadence Modus is a plus.