Design Verification Intern

About the role

Marvell develops semiconductor solutions for enterprise, cloud, AI and carrier architectures. This internship sits in a development team working on next-generation network switches, covering a wide range of IPs from definition through architecture, design and verification. The intern learns switch architecture, design and verification tools and methodologies, and does hands-on development tasks.

Key responsibilities

• Implement new features in design and verification.
• Reach high-frequency, high-performance and low-power targets.
• Write a verification test plan using random techniques and coverage analysis.
• Develop a complex object-oriented random verification environment in System Verilog/UVM.
• Create tests and tune the environment to achieve coverage goals.
• Own and debug failures in simulation to root cause problems.
• Analyze and close code and functional coverage.
• Use scripting languages to automate repetitive tasks and improve efficiency.

Required profile

• Candidate pursuing a BS/MS (preferred) degree in CS/EE or a related technical field.
• At least two years before graduation.
• Good understanding of object-oriented programming and digital logic.
• Excellent problem-solving ability and good people relations and teamwork skills.

Required skills

• System Verilog and UVM
• Python and C++
• Object-oriented programming and digital logic

The internship involves learning AI-assisted tools and verifying complex features to tapeout quality. Candidates may need access to technology subject to U.S. export control laws, and AI tools are not allowed during interviews.